1. Field of the Invention
The present invention relates to a test pattern design. In particular, the present invention relates to an ideal test key design for gate oxide thickness extraction.
2. Description of the Prior Art
The gate oxide capacitance-voltage (CV) curve provides many essential fundamentals to oxide thickness extraction, mobility calculation, metallurgical channel length determination and interface trap characterization, which are the critical parameters of advanced CMOS technology development. However, as the critical dimension decreases, the oxide thickness is aggressively scaled down (˜2.0 nm) for advanced ultra-thin oxide process development so the measured CV curve is distorted due to exponentially increasing gate leakage current and series parasitic resistance.
The following equation predicts the error ratio of the measured capacitance and the real capacitance:Cm=Cinv/{1+(Rs)/(Rp)}2 
Cinv: real capacitance/ideal capacitance
Cm: measured capacitance
Rp: total resistance of gate oxide
Rs: R1(poly resistance)+R2 (gate channel resistance)+R3 (contact and metal resustance)
It is accordingly concluded that in order to render the Cm value approach to the Cinv value as much as possible, either increasing the Rp or decreasing the Rs will do. To solve this issue, several different solutions are known.
In “A Floating Well Method for Exact Capacitance-Voltage Measurement of Nano Technology,” Hung-Der Su et al., IEEE Trans. Electron Device, Vol. 50, No. 6, p.p. 1543-1544, 2003, it mentions a two-element approach with smaller test pattern (25 μm2 with 0.4 pF total capacitance). However, even a tiny 20 fF parasitic capacitance would cause undesirable error on oxide thickness extraction.
In “Extending Two-Element Capacitance Extraction Method Toward Ultraleaky Gate Oxides Using a Short-Channel Length,” Jung-Suk Goo et al., IEEE Electron Device Letters, Vol. 25, No. 12, p.p. 819-821, 2004, it proposes using gate length shorter than 0.2 μm in parallel model for a lower channel resistance. Nevertheless it is easily understood that in practice even a 10 nm gate length variation caused by any possible imperfection could still lead 5%, an unacceptable error on oxide thickness extraction.
Therefore, a better approach is still required to minimize the error of measured thickness from process-induced gate area variation and parasitic capacitance.